Recipe for Success

Leading-edge CMOS technology is the foundation for TI’s signal processing products across the wireless, wireline and digital consumer markets. TI was among the first to enter volume manufacturing with state-of-the-art 90-nm technology on 300-mm wafers, and 65-nm production. We’re aggressively developing our 45-nm process technology today. Among the companies with the highest-performance CMOS processes, TI has established itself as an industry leader in reducing power consumption, a feature that helps prolong battery life in wireless communications and other portable applications.

Back to Top

90-nanometer CMOS

Since entering volume production with its advanced 90-nm CMOS process, we have delivered over 600--million devices built on the process with more than 60 different designs in various stages of production. This includes delivery of the industry’s first single-chip cell phone device that is enabling more cost effective, advanced wireless handsets to address the mass-market, voice-centric market. For 2.5G and 3G wireless handsets, the 90-nm process enables up to three times faster voice, video and data processing without sacrificing power consumption.

TI’s 90-nm technology cuts die size by a third while delivering smaller, higher-performance, lower-power products. Our advanced integration capacities support a wide range of analog and RF components, including TI’s unique, breakthrough DRP™, or digital radio processor, architecture that simplifies RF processing and dramatically cuts power consumption of wireless transmit and receive functions. This approach extends battery life of wireless devices and frees boards pace for enhancing the functionality of advanced multimedia devices.

With transistor gate widths as small as 37 nm, TI pushes fundamental physical laws to the known limits—all in the pursuit of greater performance which exceeds TI’s 130-nm process by over 50 percent. For the first time the 90-nm process enabled transistors with different thresholds to be instantiated on the same die, allowing TI chip designers to enhance performance of critical paths using low-threshold transistors while saving power consumption in other circuits. We optimized three different process flows: one to manufacture exceptionally high-performance products such as server microprocessors, another process for extremely low-power, portable products, and a third for devices with balanced performance and power requirements.

TI’s highest performance CMOS logic uses its industry leading, (37nm) gate length and highly effective gate dielectric scaling to reduce capacitance and increase drive current, the primary factors in transistor switching speed, which in turn determines processor operating frequency. Other improvements combining to drive performance in both the NMOS and PMOS transistors include strain induced on the transistor channel to increase electron mobility, nickel silicide to lower gate resistance, and ultra-shallow source / drain junctions.

Back to Top

65-nanometer CMOS

In early 2005, TI was first to deliver fully functional wireless digital baseband devices from its advanced 65-nm process. Since that time, 10 designs have entered production with a total of over ten-million total units shipped. The process shrinks 90-nm design area by half, boosts transistor performance by 40 percent and reduces leakage power from idle transistors by a factor of 1000.

TI’s 65-nm process combines both digital and analog functionality in tightly integrated system-on-a-chip (SoC) solutions. It incorporates several innovative power management techniques to address an increased emphasis on low power as advanced multimedia and high-end digital consumer electronics functionality is on the rise. This includes TI’s SmartReflex™ dynamic power management technologies that automatically scale power supply voltage based on user performance demands and helps control power consumption. By closely monitoring circuit speed, SmartReflex can dynamically adjust voltages to meet the exact performance requirements without sacrificing overall system performance. As a result, minimum power is used for each operating frequency, extending battery life and reducing the amount of heat produced by the device.

By leveraging new materials and innovative manufacturing techniques, TI also places an emphasis on overall chip performance in the 65-nm process. The process technology includes up to 11 layers of copper interconnect integrated with a low k dielectric, OSG, with a k of 2.8 – 2.9, as well as capacitance and propagation delays within the interconnect layers of a device. In addition, TI includes an induced strain on the transistor channel during chip processing to increase electron and hole mobility; nickel silicide to lower both gate and source / drain resistance, and ultra-shallow source / drain junctions. A unique use of differential offset spacers allows independent optimization of NMOS and PMOS transistors, driving performance and minimizing leakage.

Back to Top

45-nanometer CMOS

Introduced in June 2006, TI’s advanced 45-nm process features 193-nm immersion lithography to double the number of chips produced on each silicon wafer. Through several additional proprietary techniques, TI is driving capabilities of its system-on-chip processors to new levels, including a 30 percent increase in performance while reducing power consumption 40 percent.

These advancements in performance, power consumption and density result in smaller, faster and lower power products for TI customers. For end users, these features deliver a better overall experience, including longer battery life in portable devices and more applications running simultaneously.

TI continues to address the power consumption challenge by leveraging SmartReflex™ power and performance management technologies that were introduced at the 65-nm node, along with support of TI’s DRP™ architecture to integrate digital RF functionality in single-chip wireless solutions. The 45-nm design libraries continue to extend SoC capabilities by including a host of analog components such as resistors, inductor and capacitors that allow continued integration of formerly stand-alone functions.

The 45-nm process leverages an ultra low k dielectric with a k value of 2.5, reducing interconnect capacitance by 10 percent and boosting overall transistor performance. This is also TI’s first use of silicon-germanium in its strain application, and the company is considering techniques to cost-effectively enhance performance through use of a dual work function metal gate at some point in the 45-nm roadmap.

TI expects to sample the first SoC product in 2007.